1. Field
Exemplary embodiments of the present invention relate to a memory device and a test method thereof.
2. Description of the Related Art
Most memory devices such as DRAM (Dynamic Random Access Memory) have a repair scheme for repairing failures therein.
FIG. 1 is a block diagram illustrating a conventional memory device including a row repair scheme.
Referring to FIG. 1, the memory device includes a cell array 110 including a plurality of memory cells, a row circuit 120 for activating a word line selected by a row address R_ADD, and a column circuit for accessing a bit line selected by a column address C_ADD for reading or writing.
A row fuse circuit 140 stores a row address corresponding to a failed memory cell in the cell array 110, as a repair row address REPAIR_R_ADD. A row comparison unit 150 compares the repair row address REPAIR_R_ADD stored in the row fuse circuit 140 with the row address R_ADD input from an external source. When the repair row address REPAIR_R_ADD coincides with the row address R_ADD, the row comparison unit 150 controls the row circuit 120 to activate a redundant word line instead of the word line designated by the row address R_ADD. That is, the word line corresponding to the repair row address REPAIR_R_ADD stored in the row fuse circuit 140 is replaced with the redundant word line.
A signal RACT in FIG. 1 indicates that an active command for allowing a word line to be activated, a signal RD indicates a read command, and a signal WT indicates a write command.
The conventional row fuse circuit 140 mainly includes a plurality of laser fuses. A unit laser fuse stores ‘high’ or ‘low’ data according to whether the fuse has been cut. Programming of the laser fuse is possible only at a wafer level, that is, it is not possible to program the laser fuse at a package level. Furthermore, it is difficult to design the laser fuse to have a smaller area due to the limitation of a line pitch.
To overcome such disadvantages of the laser fuse, a nonvolatile memory, such as an efuse array circuit, a NAND flash memory, a NOR flash memory, an EPROM (Erasable Programmable Read Only Memory), an EEPROM (Electrically Erasable Programmable Read Only Memory), a FRAM (Ferroelectric RAM), or a MRAM (Magnetoresistive RAM), is mounted in a memory device, and repair information is stored in the nonvolatile memory, as disclosed in U.S. Pat. Nos. 6,940,751, 6,777,757, 6,667,902, 7,173,851, and 7269047.
FIG. 2 is a block diagram illustrating a memory device in which a nonvolatile memory is used to store repair information.
Referring to FIG. 2, the memory device includes a plurality of memory banks BK0 to BK3, registers 210_0 to 210_3 provided to the memory banks BK0 to BK3 to store repair information, and a nonvolatile memory 201.
The nonvolatile memory 201 is provided instead of the fuse circuit 140. The nonvolatile memory 201 stores repair information (i.e., repair addresses) corresponding to the memory banks BK0 to BK3. The nonvolatile memory may be one of an efuse array circuit, a NAND flash memory, a NOR flash memory, an EPROM, an EEPROM, a FRAM, and a MRAM.
The registers 210_0 to 210_3 are configured to be provided to the corresponding memory banks BK0 to BK3 and store repair information for the corresponding memory banks, respectively. That is, the register 210_0 is configured to store repair information for the memory bank BK0, and the register 210_2 is configured to store repair information for the memory bank BK2. The registers 210_0 to 210_3 include latch circuits, and are configured to store the repair information only when power is supplied thereto. The repair information to be stored in the registers 210_0 to 210_3 is received from the nonvolatile memory 201.
Since the nonvolatile memory 201 is provided in an array type, a certain time is required to call data stored therein. Thus, it may not be possible to directly perform a repair operation using the data stored in the nonvolatile memory 201. In this regard, the repair information stored in the nonvolatile memory 201 is transmitted to and stored in the registers 210_0 to 210_3, and data stored in the registers 210_0 to 210_3 is used for repair operations for the corresponding memory banks BK0 to BK3. The process, in which the repair information stored in the nonvolatile memory 201 is transmitted to the registers 210_0 to 210_3, is called boot-up, and such a boot-up operation is performed in an initialization operation of the memory device.